IIT Kharagpur

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Publications

Citations / H-Index

3420 Citations

27 h-index

3102 Citations

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1147

Google Scholar

Co-author Network

Expertise

Computer Science Hardware and Architecture

Personal Information

Dr Rajat Subhra Chakraborty

Male

Department of Computer Science and Engineering, IIT Kharagpur

Kharagpur, West Bengal, - 721302

Experience

Qualification

Patents

A METHOD AND A SYSTEM FOR EVALUTION OF REVERSIBLE WATERMARKING OF DIGITAL IMAGES AND AUDIO

ARCHITECTURE AND DESIGN AUTOMATION OF HIGH PERFORMANCE LARGE ADDERS AND COUNTERS ON FPGA THROUGH CONSTRAINED PLACEMENT

Multi-level inline data deduplication

MULTI-LEVEL INLINE DATA DEDUPLICATION

ARCHITECTURE AND DESIGN AUTOMATION OF HIGH PERFORMANCE LARGE ADDERS AND COUNTERS ON FPGA THROUGH CONSTRAINED PLACEMENT

DÉDUPLICATION DE DONNÉES EN LIGNE MULTI-NIVEAU | MULTI-LEVEL INLINE DATA DEDUPLICATION

ARCHITECTURE DE FPGA ET AUTOMATISATION DE CONCEPTION PAR LE BIAIS D'UN PLACEMENT RESTREINT | FPGA ARCHITECTURE AND DESIGN AUTOMATION THROUGH CONSTRAINED PLACEMENT

SYSTEM AND METHOD FOR DYNAMIC PARTIAL RECONFIGURATION OF CIRCUITS MAPPED OR CONFIGURED ON FPGA PLATFORM

A MULTIPLEXER BASED SYSTEM FOR ELECTRONIC DEVICE AUTHENTICATION AND PREVENTING COUNTERFEITING OF THE ELECTRONIC DEVICE

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Publications (148)

Academic Identity

Dr Rajat Subhra Chakraborty

Publications

Citations / H-Index

Altmetrics

Google Scholar

Co-author Network

Co-author - 355

Expertise

Computer Science Hardware and Architecture

Personal Information

Experience

Associate Professor

Qualification

Ph.D

Patents

MULTI-LEVEL INLINE DATA DEDUPLICATION

A METHOD AND A SYSTEM FOR EVALUTION OF REVERSIBLE WATERMARKING OF DIGITAL IMAGES AND AUDIO

ARCHITECTURE AND DESIGN AUTOMATION OF HIGH PERFORMANCE LARGE ADDERS AND COUNTERS ON FPGA THROUGH CONSTRAINED PLACEMENT

Multi-level inline data deduplication

MULTI-LEVEL INLINE DATA DEDUPLICATION

ARCHITECTURE AND DESIGN AUTOMATION OF HIGH PERFORMANCE LARGE ADDERS AND COUNTERS ON FPGA THROUGH CONSTRAINED PLACEMENT

DÉDUPLICATION DE DONNÉES EN LIGNE MULTI-NIVEAU | MULTI-LEVEL INLINE DATA DEDUPLICATION

ARCHITECTURE DE FPGA ET AUTOMATISATION DE CONCEPTION PAR LE BIAIS D'UN PLACEMENT RESTREINT | FPGA ARCHITECTURE AND DESIGN AUTOMATION THROUGH CONSTRAINED PLACEMENT

SYSTEM AND METHOD FOR DYNAMIC PARTIAL RECONFIGURATION OF CIRCUITS MAPPED OR CONFIGURED ON FPGA PLATFORM

A MULTIPLEXER BASED SYSTEM FOR ELECTRONIC DEVICE AUTHENTICATION AND PREVENTING COUNTERFEITING OF THE ELECTRONIC DEVICE

Publications (148)

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